Synchronous RNG: Device Description

The first hardware device we will consider is a synchronous random number generator. It is a simple source of random numbers that we wish to expose to user-space applications. Our RNG device is connected to the host computer (the VM in our setup) on the PCI bus. Like most approaches to random number generation in computer systems, our RNG generates sequences of random numbers that must be initialised with a seed.

It exposes only two functions accessible from the host OS through MMIO:

1. Obtaining a random number, by having the host read an MMIO register. That is the primary function of the device.
2. Seeding the random number generator, achieved by writing an MMIO register.

The device is synchronous, meaning that every operation completes immediately upon the MMIO transaction, and the host does not need to manage any asynchronous completion mechanisms.

The following document is the datasheet of our educational synchronous RNG:

🗎 EDU‑RNG‑SYNC: Educational Synchronous Random Number Generator PCI Device

Please read it carefully to get a good understanding of the device’s behaviour and the interface it exposes to the host for its operation. The datasheet gives:

• An overview of the component’s behaviour and features.
• PCI identification information, numeric values the host OS uses to recognise this specific device on the PCI bus.
• Memory map and register descriptions for MMIO.
• Further information helpful for driver development, such as predefined constants for PCI identification and register offsets from the BAR.